-------------------------------------------------------------------------------
-- datapath_tb.vhd
-------------------------------------------------------------------------------
--
-- This file is part of SKUMLI.
-- Copyright (C) 2011 Davide Giuseppe Monaco (black.ralkass@gmail.com)
--
-- SKUMLI is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- SKUMLI is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with SKUMLI.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.datapath_pack.all;
use work.control_unit_pack.all;
-------------------------------------------------------------------------------
entity datapath_tb is
end datapath_tb;
-------------------------------------------------------------------------------
architecture test_bench of datapath_tb is

  signal T_clk           : std_logic;                         -- clock
  signal T_rst           : std_logic;                         -- reset
    
  -- control signals
  signal T_m_pc_din_sel  : std_logic_vector(1 downto 0);  -- mux pc data in
  signal T_cu_zero       : std_logic;                     -- pc we alu zero
  signal T_branch        : std_logic;                     -- pc we alu zero
  signal T_pc_we_s       : std_logic;                     -- pc we signal
  signal T_ca_addr_sel   : std_logic_vector(1 downto 0);
  signal T_m_cc_addr_sel : std_logic;                     -- mux cc address
  signal T_ca_we         : std_logic;                     -- current addr we
  signal T_cc_rw         : std_logic;                     -- cc read/write (L/H)
  signal T_cc_cs         : std_logic;                     -- cc chip select
  signal T_md_we         : std_logic;                     -- md we
  signal T_m_data_sel    : std_logic;                     -- mux regfile data in
  signal T_ir_we         : std_logic;                     -- ir we
  signal T_alu_out_we    : std_logic;                     -- alu in we
  signal T_tg_we         : std_logic;                     -- target we
  signal T_alu_op        : std_logic_vector(1 downto 0);  -- alu operation
  signal T_m_opd_b_sel   : std_logic_vector(1 downto 0);  -- mux alu operand b
  signal T_m_opd_a_sel   : std_logic;                     -- mux alu operand a
  signal T_opd_b_we      : std_logic;                     -- operand B register we
  signal T_opd_a_we      : std_logic;                     -- operand A register we
  signal T_rf_we         : std_logic;                     -- rf we
  signal T_m_rd_sel      : std_logic;                     -- mux rf RD in

  -- out signals
  signal T_cc_rdy        : std_logic;                     -- cc ready
  signal T_opcode        : std_logic_vector(5 downto 0);  -- instruction opcode

begin -- test_bench
-------------------------------------------------------------------------------
  CU : control_unit
    port map (
      T_clk, T_rst,
      T_cc_rdy,
      T_opcode,
      T_m_pc_din_sel,
      T_cu_zero, T_branch, T_pc_we_s,
      T_ca_addr_sel, T_ca_we, 
      T_m_cc_addr_sel,
      T_cc_rw, T_cc_cs,
      T_md_we,
      T_m_data_sel,
      T_ir_we,   
      T_alu_out_we,
      T_tg_we,   
      T_alu_op,
      T_m_opd_b_sel, T_m_opd_a_sel,
      T_opd_b_we,
      T_opd_a_we,    
      T_rf_we,     
      T_m_rd_sel
    );

  DP : datapath
    port map (
      T_clk, T_rst,
      T_m_pc_din_sel,
      T_cu_zero, T_branch, T_pc_we_s,
      T_ca_addr_sel, T_ca_we, 
      T_m_cc_addr_sel,
      T_cc_rw, T_cc_cs,
      T_md_we,
      T_m_data_sel,
      T_ir_we,   
      T_alu_out_we,
      T_tg_we,   
      T_alu_op,
      T_m_opd_b_sel, T_m_opd_a_sel,
      T_opd_b_we,
      T_opd_a_we,    
      T_rf_we,     
      T_m_rd_sel,
      T_cc_rdy,
      T_opcode
    );
-------------------------------------------------------------------------------
  process
  begin
    T_clk <= '0';
    wait for 5 ns;
    T_clk <= '1';
    wait for 5 ns;
  end process;
-------------------------------------------------------------------------------
  test: process
  begin -- test

    T_rst    <= '1', '0' after 1 ns;

    wait for 10000 ns;

  end process test;
-------------------------------------------------------------------------------
end test_bench;
